1. Field of the Invention
This invention relates to a process for manufacturing semiconductor structure or devices, more particular for growing a high quality Ge film on Si substrate using a novel GeSi buffer method and additionally growing a high quality Group III-V, such as GaAs epitaxial layer on the grown Ge/SiGe/Si substrate.
2. Description of Related Art
The growth of high quality GaAs or other III-V compound semiconductors on silicon substrate is recognized as a desirable goal for the fabrication of advanced semiconductor devices. Specific advantages of this combination of materials include the availability of GaAs with high electron mobility and optical activity on a silicon substrate with improved mechanical strength and thermal conductivity over that obtainable with GaAs substrate. In addition, the growth of high quality GaAs on silicon offers the possibility of monolithically integrating GaAs and silicon devices for advanced electronic components.
However, one of the key limitations in the implementation of device structure based on heteroepitaxial GaAs on silicon has a 4.0% difference in lattice constant and additional intrinsic thermal conductivity difference between the two different materials. This lattice mismatch leads to the formation of a network of misfit dislocation at the heterointerface and high density threading dislocation in the epitaxial layers.
Presently public techniques to overcome the defects produced from the growth of GaAs on Si substrate include varying epitaxial growth conditions for directly growing GaAs epitaxy on Si, applying strained supper lattices buffer to filter threading dislocation and using Ge composition graded SiGe layers as buffer.
For example, the techniques for directly growing GaAs epitaixial layer on Si, for the purpose of lowering the large threading dislocation due to lattice mismatch of GaAs on Si substrate, two steps of annealing methods or strained super-latticed buffer are previously applied to solve those problems. Related disclosures include U.S. Pat. Nos. 5,959,308, 5,879,962, 5,473,174, 5,308,444, 5,438,951, 5,238,869, 5,183,776 and 5,141,893, furthermore, it is reported in “Subpicosecond carrier dynamics in low-temperature grown GaAs on Si substrates” (Applied Physics Letters, Vol. 75, No. 17, 25 Oct. 1999) from A. C. Gossard et al., and in “Growth of high quality gallium arsenide on HF-etched silicon by chemical beam epitaxy” (Applied Physics Letters, Vol. 62, No. 14, 5 Apr. 1993) from P. J. Goodhew et al., and in “Integration of low-temperature GaAs on Si substrates” (Applied Physics Letters, Vol. 62, No. 3, 18 Jan. 1993) from T. F. Carruthers et al. These prior arts have less effects on lowering the threading dislocation density according to the techniques for production from the directly growing GaAs on Si, wherein the threading dislocation density is generally about 108/cm2, and further reduced to about 107/cm2 with an additional annealing. Furthermore, due to large difference between thermal expansion coefficient of GaAs and that of Si, it is difficult to remove the additional dislocation induced during annealing, thus, these arts obviously are not deemed to be used for fabricating of high performance device.
Furthermore, the technique which uses interlayer as buffer for growing GaAs on Si, that is, a structure of GaAs/interlayer/Si, as we know the interlayer can include SeS2, ZnSe or STO film. For example, an bonding technique disclosed in “High-quality GaAs on Si substrate by the epitaxial lift-off technique using SeS2” (Applied Physics Letters, Vol. 75, No. 24, 13 Dec. 1999) from M. Umeno et al., which describes that a GaAs wafer is bonded to silicon substrate using SeS2 as the interlayer and the desirable GaAs layer is acquired by applying the lift-off technique. However, these arts obviously make some problems, such as high fabricating cost and no large scale of GaAs epitaxy on Si substrate to be obtained.
And, the reference “Use of ZnSe as an interlayer for GaAs growth on Si” (Applied Physics Letters, Vol. 61, No. 2, 13 Jul. 1992) from J. C. Tramontana et al. is reported that ZnSe is used as the interlayer for growing GaAs epitaxy on Si, i.e., the interlayer has a structure of GaAs/ZnSe/Si. However, it is difficult to grow a high quality ZnSe on Si, and the small thermal conductivity of ZnSe is disadvantageous for fabricating of device, thus, the utilization of this invention is in the presence of some problems to be solved.
In addition, it is reported in “New research yield epitaxial grown GaAs on Si” (Solid State Technology, 45, 61 2002) from K. Esenbeiser et al., which discloses the use of STO film as the interlayer for growing GaAs epitaxy on Si, i.e., a structure of GaAs/STO film/Si. However, it is with high fabricating cost and low productivity for growth by applying molecule beam epitaxy (MBE), and additionally it is with small thermal conductivity of STO film, which is disadvantageous for heat diffusion of device, thus, the utilization of this invention totally is in the presence of some problems to be solved, too.
As for applying the technique in using Ge composition graded buffer for growing SiGe epitaxy, which is disclosed in “Novel dislocation structure and surface morphology effects in relaxed Ge/SiGe(graded)/Si structures” from E. A. Fitzgerald et al. mentioned above, wherein graded Si1-xGex is applied as interlayer for the growth of GaAs epitaxy on Si due to almost the same lattice constant and thermal expansion coefficient for the two different materials, this technique has comparatively wide field in application, but is also in the presence of some problems to be overcome. That is, applying the concept of gradually increasing Ge content of SiGe epitaxy, since the Ge composition starts from zero to a very high value and herein forms the crosshatch pattern, where the pattern brings a very high surface roughness. As for growing under the condition that the Ge epitaxial layer is 6 degree oriented to silicon substrate, the roughness is over 150 Å; comparatively, it gains a surface roughness of over 450 Å for growing without degrees. Wherein, high surface roughness due to thick epitaxial layer and cross hatch pattern will increase the fabrication cost of epitaxy and cause difficulties in device producing. As for removing cross hatch pattern, chemical-mechanical polishing (CMP) is subjected to solve these problems in above-mentioned references and patents, but it increases additional cost and causes difficulties in processing substantially.